MAX5877EGK+D【PDF 6/19 页】IC DAC 14BIT DUAL 250MSPS 68-QFN

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MAX5877

14-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

______________________________________________________________________________________

CMOS-Compatible Digital Inputs

Input Data Format Select (TORB)

The TORB input selects between two’s-complement or

offset binary digital input data. Set TORB to a CMOS-

logic-high level to indicate a two’s-complement input

format. Set TORB to a CMOS-logic-low level to indicate

an offset binary input format.

Power-Down Operation (PD)

The MAX5877 also features an active-high power-down

mode that reduces the DAC’s digital current consump-

tion from 34mA to less than 5A and the analog current

consumption from 82mA to less than 2A. Set PD high

to power down the MAX5877. Set PD low for normal

operation.

When powered down, the MAX5877 reduces the overall

power consumption to less than 16W. The MAX5877

requires 10ms to wake up from power-down and enter

a fully operational state. The PD integrated pulldown

resistor activates the MAX5877 if PD is left floating.

Applications Information

CLK Interface

The MAX5877 features a flexible differential clock input

(CLKP, CLKN) with a separate supply (AVCLK) to

achieve optimum jitter performance. Use an ultra-low

jitter clock to achieve the required noise density. Clock

jitter must be less than 0.5psRMS for meeting the speci-

fied noise density. For that reason, the CLKP/CLKN

input source must be designed carefully. The differen-

tial clock (CLKN and CLKP) input can be driven from a

single-ended or a differential clock source. Differential

clock drive is required to achieve the best dynamic

performance from the DAC. For single-ended opera-

tion, drive CLKP with a low noise source and bypass

CLKN to GND with a 0.1F capacitor.

Figure 6 shows a convenient and quick way to apply a

differential signal created from a single-ended source

(e.g., HP 8662A signal generator) and a wideband trans-

former. Alternatively, these inputs can be driven from a

CMOS-compatible clock source; however, it is recom-

mended to use sinewave or AC-coupled differential

ECL/PECL or LVDS drive for best dynamic performance.

110

DECODE

LOGIC

B13P–B0P,

SELIQP

B13N–B0N,

SELIQN

CLOCK

MAX5877

Figure 5. Simplified LVDS-Compatible Digital Input Structure

DIGITAL INPUT CODE

OFFSET BINARY

TWO’S COMPLEMENT

OUT_P

OUT_N

00 0000 0000 0000

10 0000 0000 0000

IOUTFS

01 1111 1111 1111

00 0000 0000 0000

IOUTFS / 2

11 1111 1111 1111

01 1111 1111 1111

IOUTFS

Table 2. DAC Output Code Table

WIDEBAND RF TRANSFORMER

PERFORMS SINGLE-ENDED-TO-

DIFFERENTIAL CONVERSION

SINGLE-ENDED

CLOCK SOURCE

(e.g., HP 8662A)

GND

1:1

CLKP

CLKN

TO DAC

0.1

Figure 6. Differential Clock-Signal Generation

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